Study of First-Order Thermal Sigma-Delta Architecture for Convective Accelerometers

This paper presents the study of an original closed-loop conditioning approach for fully-integrated convective inertial sensors. The method is applied to an accelerometer manufactured on a standard CMOS technology using an auto-aligned bulk etching step. Using the thermal behavior of the sensor as a summing function, a first order sigma-delta modulator is built. This "electro-physical" modulator realizes an analog-to-digital conversion of the signal. Besides the feedback scheme should improve the sensor performance.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838

Investigation of the power-clock network impact on adiabatic logic

International audienceAdiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the power-clock network still remains to be studied. In this paper, we investigate the power-clock network effect on adiabatic energy dissipation. We derive closed-form analytical formulas to represent the output signal voltage and energy dissipation while taking into account the parasitic impedance of the power-clock network with respect to switching frequency such that adiabatic conditions are still met. Experiments, based on simulation, show that the power-clock network impacts both the energy efficiency of the circuit and its frequency

Impact of Technology Spreading on MEMS design Robustness

International audienc

Design for Manufacturing of MNT-based Systems: a test case

National audienc

Protection des circuits intégrés CMOS profondément submicroniques contre les décharges électrostatiques

La première partie de ce manuscrit rappelle l'implication des décharges électrostatiques au sein des circuits CMOS submicroniques, les moyens d'évaluation de la protection d'un circuit ainsi que les différentes stratégies de protection couramment employées pour protéger un circuit vis-à-vis des décharges électrostatiques et présente également les résultats silicium obtenus des structures de test utilisant le bipolaire parasite comme élément de protection (ggNMOS, LVTpnp). Par la suite, notre travail s'est concentré principalement sur la conception et le développement des protections centrales utilisant la conduction MOS pour évacuer les décharges électrostatiques. Nous apportons notamment une amélioration significative vis-à-vis des déclenchements intempestifs causés par les phénomènes de bruit rencontrés sur les alimentations, un dimensionnement robuste du circuit de déclenchement ainsi qu'une approche permettant de s'affranchir des effets néfastes rencontrés lors de mise sous tension très lente du circuit sont proposés. Par la suite nous présentons une méthode de conception d'une protection centrale dynamique associée à la présentation d'un flot global de caractérisation automatisé dans le cadre de l'utilisation d'une stratégie de protection globale d'un circuit. La dernière partie du manuscrit présente deux nouvelles approches de détection permettant d'adresser des rampes de mise sous tension très rapides sans provoquer le déclenchement de la protection pouvant induire une consommation statique critique du circuit.The first part of this thesis recalls the involvement of electrostatic discharge within submicron CMOS circuits, ways of assessing the protection of a circuit and the different protection strategies commonly used to protect a circuit against ESD events and also presents the results obtained silicon structures test using the parasitic bipolar as a protective element (ggNMOS, LVTpnp). Since then, our work has focused on design and development of protections central conduction using MOS devices to evacuate ESD current. We bring a significant improvement in particular with untimely triggers caused by the phenomena of noise encountered on power supplies. A robust design of the circuit and a trigger approach to overcome the adverse effects encountered with very slow supply ramp-up. Thereafter we propose a method for the design of a central dynamic protection associated with the submission of a comprehensive flood automated characterization in the context of the use of a comprehensive strategy for the protection of a circuit. The last part of this work proposes two new approaches regarding detection function which could make ramps power up very fast without causing the outbreak of protection that can lead to a static critical current consumption.MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF

Le thyristor parasite en technologie CMOS (application à la protection contre les décharges électrostatiques)

MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF

EDITORIAL du Numéro spécial JЗEA dédié aux JPCNFM’2016

International audienc

Méthodes alternatives pour le test et la calibration de MEMS (application à un accéléromètre convectif)

Le test et la calibration des MEMS sont des enjeux complexes à cause de leur nature multi-domaines. Ils nécessitent l'application de stimuli physiques, en utilisant des équipements de test coûteux, afin de tester et de calibrer leurs spécifications. L'objectif de cette thèse est de développer des méthodes alternatives et purement électriques pour tester et calibrer un accéléromètre MEMS convectif. Premièrement, un modèle comportemental du capteur est développé et validé en se basant sur des simulations FEM. Il inclut l'influence de tous les paramètres géométriques sur la sensibilité du capteur. Deuxièmement, le modèle est utilisé pour simuler des fautes dans le but d'identifier la corrélation qui peut exister entre la sensibilité du capteur à l'accélération et certains paramètres électriques. Troisièmement, cette corrélation est exploitée pour développer des méthodes de test et de calibration alternatives où la sensibilité est estimée en effectuant uniquement des mesures électriques et sans appliquer de stimuli physiques (accélérations). L'efficacité de ces méthodes est ainsi démontrée. Finalement, deux architectures permettant l'auto-test et l'auto-calibration sur puce sont proposées.MEMS test and calibration are challenging issues due to the multi-domain nature of MEMS devices. They therefore require the application of physical stimuli, using expensive test equipments, to test and to calibrate their specifications. The main objective of this thesis is to develop alternative electrical-only test and calibration procedures for MEMS convective accelerometers.First, a behavioral model that includes the influence of sensor geometrical parameters on sensitivity is developed and validated with respect to FEM simulations. Second, the model is used to perform fault simulations and to identify correlation that may exist between device sensitivity to acceleration and some electrical parameters. Third, this correlation is exploited to develop alternative test and calibration methods where the sensitivity is estimated using only electrical measurements and without applying any physical stimulus (acceleration). The efficiency of these methods is demonstrated. Finally, two architectures that allow on-chip test and calibration are proposed.MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF

Special issue on Design, Test, Integration and Packaging of MEMS and MOEMS (DTIP 2016): Budapest, Hungary, May 30–June 2, 2016

International audienceThe 2016 edition of the symposium on Design, Test, Integration and Packaging of MEMS and MOEMS (DTIP), the premier MEMS scientific annual event in Europe, was held in Budapest, Hungary, May 30–June 2, 2016. DTIP’2016, organized by Prof. Marta Rencz and her team from Budapest University of Technology and Economics was the 18th edition and has been extremely appreciated by an hundred of attendees for the quality of both scientific and social programs. Oral and poster presentations were carefully selected by the Program Committee to insure a high scientific level. This symposium brought together participants interested in manufacturing of microstructures and/or in design tools and methods to facilitate the design of these microstructures.This special issue is composed of 24 extended versions of the best papers presented at the symposium. Extended papers have been refereed, along the usual refereeing process in force at Microsystem Technologies. Selected papers, out of 33 proposals, cover a broad range of topics including CAD tools, design methods, multi-physics modelling, thermal evaluation and optimization; test, reliability and failure analysis; sensors and actuators; advances in micro-fabrication, integration and packaging; new materials; advanced characterization techniques.We hope that you will enjoy these contributions as much as we did and if you want to join the DTIP community don’t hesitate to attend our next event or to visit our website

Analog and Mixed-Signal Test Bus: IEEE 1149.4 Test Standard

International audienc